1. Field of the Invention
The present invention is in the field of electronic technology and, in particular, relates to a process for making multilevel interconnections of electronic components.
2. Description of the Background Art
Methods of making multilevel interconnections of electronic elements, and particularly, methods of forming an aluminum interconnect structure on an integrated circuit chip, are known. For example, U.S. Pat. No. 4,158,613, beginning at col. 3, line 50, discloses the formation of each level of a multilevel interconnect structure by way of deposition of an aluminum layer onto a substrate, forming a refractory metal layer over the aluminum along the lines where an interconnect is to be formed, anodizing both the exposed aluminum and the surface of the refractory metal layer so as to form the interconnect structure under the refractory metal layer, and removing the thin layer of the anodized refractory metal.
More specifically, as disclosed in U.S. Pat. No. 4,158,613, an aluminum interconnect layer is deposited on a dielectric layer, a thin layer of tantalum or other refractive metal is deposited over the aluminum in those areas where the interconnects are to be formed, the tantalum layer is patterned with a negative photoresist which forms a blocking mask over the tantalum in a pattern of the interconnect structure to be formed, and the exposed tantalum is etched in a carbon tetrafluoride plasma to form a structure where the remaining portions of tantalum define the aluminum interconnect structure to be finally achieved. The photoresist is removed, the bare tantalum and aluminum layers are anodized simultaneously in a phosphoric or oxalic electrolyte under conditions such that the tantalum will only form a barrier type anodic film while the exposed aluminum layer is completely anodized to form a dielectric porous anodic material down to the dielectric layer thereby defining the aluminum interconnect structure. The tantalum oxide barrier anodic film is then etched away by carbon tetrafluoride plasma leaving behind the unanodized tantalum layer. Other less preferred refractory metals which may be used include niobium and hafnium.
The above procedure provides a method by which it becomes possible to obtain an interconnected multilevel system of electronic elements on semiconductor substrates.
However, in the case of anodizing a metal formed over an insulative substrate, there arises the problem of supplying voltage to the metal regions to be oxidized. In the porous anodization of aluminum down to the insulative substrate surface, the thinning of the aluminum layer through which the voltage is supplied leads to an increase in the voltage drop on the thinning aluminum layer and to a decrease in the anodization voltage. Therefore, the through-oxidation rate will be higher in those regions of the aluminum layer which are nearer to the region of the anodization voltage supply. This phenomenon will lead to a voltage cutoff in the farther regions of the aluminum layer and to the formation of non-oxidized regions of the aluminum layer between the interconnect lines of the level. As a result, shorts may appear between the lines, and the parameters of the intercomponent insulation and their reproducibility may deteriorate.
Moreover, in the deposition of the refractory-metal layer onto the aluminum layer and in the subsequent processing steps, the aluminum and the refractory-metal layers interact to form unanodizable intermetallic compounds in non-pattern areas which degrades the insulating parameters of the intercomponent and interlevel insulation, and lowers the temperature-effect resistance and the reliability of the multilevel system.
As disclosed in DD-A 272755, another method of making a multilevel system of electronic parts is known which involves the formation of each level of an interconnect system by depositing an aluminum layer onto a previously prepared substrate surface, forming a blocking mask in a pattern of the level interconnect lines upon the above-mentioned aluminum layer, carrying out porous anodizing of the exposed aluminum, removing the blocking mask, depositing the next aluminum layer, forming a blocking mask in a pattern of the contact vias to the next level, and carrying out porous anodization.
More specifically, the method disclosed in DD-A 272755 may be realized in the following way. An adhesive nichrome sublayer and an aluminum layer are deposited onto an insulative substrate surface. A porous oxide is formed over the entire aluminum surface which is subsequently boiled in water. An aluminum layer is deposited onto the thus prepared substrate, and a blocking photoresist mask is formed in a pattern of the level interconnect lines on the above-mentioned aluminum layer. The unprotected areas of the aluminum layer are subjected to porous full-depth anodization. Then, the photoresist mask is removed, and the porous aluminum oxide is sealed in boiling water. A further aluminum layer is deposited, and a photoresist mask in a pattern of the contact vias to the next layer is formed upon it. Porous anodization of this aluminum layer is carried out followed by the removal of the photoresist mask and the seal treatment in boiling water. The subsequent levels of the interconnections are formed in the same way.
The method of DD-A 272755 has a number of disadvantages. Firstly, the sealing of the porous oxide in boiling water results in deterioration of the insulating properties of the aluminum oxide and in the reduction of its resistance to mechanical and temperature effects due to its hydration.
Secondly, the use of the aluminum single-layer oxide as interlevel insulation causes reduced reliability of the interconnect system of the electronic parts due to the existence of the hydrated porous aluminum oxide in the positions of the crossovers of different-level interconnect lines. The hydrated porous aluminum oxide has a low breakdown voltage, as well as insufficient time and thermal stability characteristics.
Thirdly, in forming contact vias to the next level by the process of depositing an additional aluminum layer and porous anodization thereof, there is the risk of oxidation of the previously formed interconnect lines due to the absence of a protective layer on their surfaces, the effect being compounded by the differences in the rates of the porous anodization over the substrate area and due to the thickness non-uniformity of the aluminum layers being deposited. These factors may cause breaks in the lines, decrease of the cross-sections of the lines, and, hence, decrease of the electrical conductivity and intensity of electromigration. All this reduces the reliability of the interconnect system, the reproducibility of its parameters and the accuracy of the geometric sizes and, also, complicates the control and monitoring processes.
Moreover, during the porous anodization process when forming contact vias to the next level, the photoresist mask edges are undermined because of the bulk growth of the porous oxide. Further, electrolyte leaks may occur under the photoresist mask to cause the total stripping of the mask. The result is a decrease in the contact via areas due to the oxidation of some part of their surfaces, and hence an increase in the resistance of the contact vias, or even a break in contact.
As disclosed in JP-B 56-43637, a further method of making a multilevel interconnected system of electronic parts is known, which involves the formation of each level of the system by way of depositing an aluminum layer on a substrate surface, forming a blocking mask leaving exposed the intended pattern of the level lines upon the above mentioned layer, carrying out barrier anodization, removing the blocking mask, and carrying out porous anodization.
More specifically, the method of JP-B 56-43637 is realized in the following way. An aluminum layer is deposited on a previously cleaned surface, and a blocking mask leaving exposed the pattern of the level lines is formed upon the above-mentioned layer. Then, a barrier aluminum oxide is formed in a solution of ammonium pentaborate in ethylene glycol, at voltages ranging from several tens to several hundred volts. The barrier aluminum oxide is formed at the interconnect lines and at those areas of the aluminum layer which are at the anodizing electrolyte interface. After the blocking mask has been removed, the process of porous anodization is carried out in an aqueous solution of sulfuric acid at a voltage of not more than the half value of the voltage applied in the formation of the barrier aluminum oxide. A photoresist mask is formed and the barrier aluminum oxide is selectively etched to remove the oxide and expose the aluminum surface to make contact vias to the next level. The subsequent levels of the interconnect system of electronic parts are formed in the same way.
The method of JP-B 56-43637 allows the making of a multilevel interconnected system of electronic parts both on a semiconductor and on an insulative substrate. However, the method has the following disadvantages.
First, the interlevel isolation consists of only a thin, barrier aluminum oxide which cannot be obtained thicker than 0.2-0.25 .mu.m. Such a thin barrier aluminum oxide layer has low breakdown voltages, small mechanical strength and a large probability of pinholes resulting in reduced thermal and mechanical stability and reliability of this interconnect system of electronic parts.
Second, in the regions of the interconnect line crossovers, large stray capacitances appear, as the permittivity of the barrier aluminum oxide is in the range of about 8-9, thereby degrading the frequency characteristics and functional usefulness of the system.
Further, the method does not produce a reliable electrical insulation between the lines of the same level, since in the process of porous anodization of the aluminum layer, a redistribution and cutoff of the anodizing voltage occurs in the regions farthest from the contact area, and it leads to the appearance of non-oxidized portions. This deteriorates the intercomponent insulation, particularly on substrates with rough surfaces and with thickness non-uniformity of the aluminum layer over the substrate area.
Besides, in the process of porous anodization, the rate of the aluminum oxide growth deep into the metal decreases with a decrease in spacing between the lines in the level. This results in non-oxidized portions between the interconnect lines with the smaller spacing deteriorating the insulating properties of the intercomponent insulation.
Further yet, the use of the chemical etch step leads to additional contamination of the layers by the etch process products, and it degrades the insulating properties of the intercomponent and interlevel insulation, complicates the technological process and causes ecological problems.
In the formation of a blocking photoresist mask upon the surface of a porous aluminum oxide, the photoresist penetrates into the bulk of the porous insulator and is not totally removed, even by plasma chemical stripping of the photoresist. The organic substance residues inside the porous oxide degrades the adhesion of the aluminum layers in the subsequent deposition of them and deteriorate the reproducibility and reliability parameters of the multilevel interconnection system.
A further disadvantage of the method of JP-B 56-43637 lies in the non-planarity of the surface of each level due to the bulk growth of the porous oxide, this non-planarity being especially obvious when thick aluminum layers are used. The non-planarity of the level surface can lead to the thinning and breaking of the next-level interconnect lines where the lines bend at the pattern steps, significantly reducing the reliability of the multilevel interconnected system.
U.S. Pat. No. 3,988,214 (Tsunemitsu '214) and divisional U.S. Pat. No. 4,001,871 (Tsunemitsu '871) teach an integrated circuit device wherein multi-level interconnections of the wiring structure are formed by selective anodization of aluminum into insulating structures, leaving conductive non-anodized channels. As can be seen in FIG. 4 of these patents, an aluminum film is deposited on a substrate. The aluminum surface is covered with a photoresist, leaving exposed the areas in which the wiring layer is to be formed, and anodic oxidation is carried out using constant voltage with ammonium borate saturated ethylene-glycol, so that the exposed surface of the aluminum film is selectively covered by a non-porous alumina (FIG. 4(C)). The photo-resist is removed (FIG. 4(D)). The non-porous alumina layer serves as a mask against further anodization when the unmasked aluminum 404 is changed to porous alumina 404 (FIG. 4(E') using 2-5% acid applied to the aluminum at a constant 20 volts. FIGS. 5(A)-(E') show the formation of porous alumina (FIG. 5(C), depositing a resist over the exposed metal where it is desired to have an interconnect (FIG. 5(D'), and hard anodizing the exposed aluminum to form a hard anodized interlevel insulator layer and exposed interconnects ("electrode lead-out portion on the surface of the aluminum film" col. 6, lines 22-23).
The semiconductors formed in accordance with these patents suffer the same disadvantages as associated with JB-B 56-43637 discussed above. First, the interlevel isolation consists of only a thin, hard aluminum oxide, which has low breakdown voltages, small mechanical strength and a large probability of pinholes resulting in reduced thermal and mechanical stability and reliability of this interconnect system of electronic parts. Second, in the regions of the interconnect line crossovers, large stray capacitances appear, as the permittivity of the hard aluminum oxide is 9-11, thereby degrading the frequency characteristics and functional usefulness of the system.
Further, the method does not produce a reliable electrical insulation between the lines of the same level, since in the process of porous anodization of the aluminum layer, a redistribution and cutoff of the anodizing voltage occurs in the regions farthest from the contact area, and it leads to the appearance of non-oxidized portions. This deteriorates the intercomponent insulation, particularly on substrates with rough surfaces and with thickness non-uniformity of the aluminum layer over the substrate area. Besides, in the process of porous anodization, the rate of the aluminum oxide growth deep into the metal decreases with a decrease in spacing between the lines in the level. This results in non-oxidized portions between the interconnect lines with the smaller spacing deteriorating the insulating properties of the intercomponent insulation.
Most semiconductor packages are manufactured in accordance with the following procedures. A semiconductor chip is attached on paddles of a lead frame and then wire bonding is carried out between inner leads of the lead frame and pads on the semiconductor chip. The wire bonded semiconductor and lead frame are molded by molding resin. Thereafter, the resulting product is subjected to deflash, trimming and forming procedures so that outer leads of the lead frame are protruded from the molded resin and then bent into predetermined shape respectively.
The semiconductor package prepared as described above have outer leads protruded from the mold resin. The outer leads are formed into a certain shape and then mounted on a printed circuit board.
However, the prior semiconductor packages have various disadvantages as follows. The prior semiconductor packages occupy large space due to the outer leads protruded from mold resins when the semiconductor packages are mounted on printed circuit boards.
Since the semiconductor packages suffer outer mechanical shock during their forming procedure, fine gaps may occur in contact areas between outer leads protruded from package bodies and mold resins, thereby causing humidity resistant property to be deteriorated due to the gaps.
Also, since the semiconductor packages require a trimming step and a forming step after a molding procedure, the manufacturing process of the packages becomes complicated with resulting increased manufacturing costs and decreased yields.
The above packages also typically utilize a heat sink member which is thermally coupled to the package's chip, the heat sink being located slightly above the chip and provided with a good thermal path to the chip to enhance heat removal from the completed package (most particularly the chip) during package operation. Such heat sinks usually comprise a metallic element located on the package in such a position as to facilitate thermal removal by interaction with a cooling airflow or, simply, relatively non-moving ambient air. The heat sink may be attached to the chip with an appropriate thermal adhesive, several of which are known in the art. To further promote heat removal, the heat sink typically includes appropriate fins, pins, or the like at various locations. The heat sink may also be of a multilayer (or multilevel) design, where each level of the heat sink is optimized for a particular function. The first level of the heat sink may be designed to optimize the thermal contact with the chip and the removal and spreading of heat from the chip, along with the function of protecting the chip and attached circuitry from chemical or other contact from various manufacturing processes. The heat sink's second level may be optimized for thermal interaction with cooling fluid flow (gas or liquid) to provide additional thermal efficiency if demanded by a particular application. This second level of the heat sink may be a separate element, attached to the first level structure by thermal adhesive. It is possible that the first heat sink level may comprise a low-profile, platelike member with the second level including a plurality of fins so that in combination, very high rates of heat removal may be realized. However, if very high thermal performance is not needed, the second level of heat sink may be omitted.
It is believed that an electronic package assembly possessing the above and other advantageous features which is thus capable of overcoming the several aforementioned problems, and a method of making such a package assembly, would constitute significant advancements in the art.
It is, therefore, a primary object of the present invention to enhance the art of electronic packages and particularly those packages for use in the computer industry.
It is another object of the invention to provide an electronic package which overcomes the aforementioned disadvantages of various known packages.
It is a still further object of the invention to provide an electronic package which can be produced in a relatively inexpensive manner, and which is adaptable to mass production techniques for such packages.
It is yet another object of the invention to provide a semiconductor package which is designed to occupy small space required to be mounted on a printed circuit board and to reduce manufacturing cost by omitting manufacturing procedures next to a molding procedure.
Another object of the invention is to provide a semiconductor package which has improved lead conductance and thus electrical property by reducing length between its inner leads and outer leads.
In accordance with another aspect of the invention, there is provided a method of making an electronic package which comprises the steps of defining routing layers by forming a blocking mask on an aluminum substrate, the blocking mask leaving exposed areas corresponding to the routing layers, the blocking mask also leaving exposed a frame around the routing layers, carrying out a barrier anodization process on the aluminum substrate to form a surface barrier oxide over the routing layers and a surface barrier oxide defining a frame around the routing layers, removing the blocking mask, providing an upper aluminum layer over the aluminum substrate, defining vias within the area defined by the frame by providing on the upper aluminum layer a blocking mask with exposed areas defining the vias, the blocking mask leaving exposed a frame around the routing layers and vias and corresponding to the frame formed on the aluminum substrate, carrying out a barrier anodization process on the upper aluminum layer to form a surface barrier oxide defining the vias and the frame on the upper aluminum layer, forming a photoresist mask in a pattern defining vias, subjecting both the aluminum substrate and the upper aluminum layer to porous anodization, and removing the photoresist mask and surface barrier oxide over the upper aluminum layer, attaching a die to the aluminum substrate, and the die being operatively electrically connected to the aluminum substrate.
In accordance with another aspect of the invention, there is provided a method of making an electronic package which comprises the steps of providing a main aluminum layer over a substrate surface, defining routing layers by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the routing layers, the blocking mask also leaving exposed a frame around the routing layers, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the routing layers and a surface barrier oxide defining a frame around the routing layers, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining vias within the area defined by the frame by providing on the upper aluminum layer a blocking mask with exposed areas defining the vias, the blocking mask leaving exposed a frame around the routing layers and vias and corresponding to the frame formed on the main aluminum layer, carrying out a barrier anodization process on the upper aluminum layer to form a surface barrier oxide defining the vias and the frame on the upper aluminum layer, forming a photoresist mask in a pattern defining vias, subjecting both the main aluminum layer and the upper aluminum layer to porous anodization, and removing the photoresist mask and surface barrier oxide over the upper aluminum layer, attaching a die to the substrate, and the die being operatively electrically connected to the substrate.
In accordance with another aspect of the invention, there is provided a method of making an electronic package which comprises the steps of providing an aluminum substrate, selectively masking the aluminum substrate, carrying out a barrier anodization process on the aluminum substrate to form a surface barrier oxide on the aluminum substrate, removing the mask, providing an upper aluminum layer over the aluminum substrate, selectively masking the upper aluminum layer, subjecting both the aluminum substrate and the upper aluminum layer to porous anodization, attaching a die to the aluminum substrate, and the die being operatively electrically connected to the aluminum substrate.
In accordance with another aspect of the invention, there is provided a method of making an electronic package which comprises the steps of providing a main aluminum layer over a substrate surface, selectively masking the substrate, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide on the main aluminum layer, removing the mask, providing an upper aluminum layer over the main aluminum layer, selectively masking the upper aluminum layer, subjecting both the main aluminum layer and the upper aluminum layer to porous anodization, attaching a die to the substrate, and the die being operatively electrically connected to the substrate.
Therefore, it is an object of this invention to provide an improvement which overcomes the aforementioned inadequacies of the prior art devices and provides an improvement which is a significant contribution to the advancement of the process for making multilevel interconnections of electronic components art.
Another object of this invention is to provide a process by which it becomes possible to reliably obtain a planar multilevel system of electronic-element interconnections with high insulting properties of the intercomponent and interlevel insulation, a planarity of each level surface, high reliability and reproducibility of electrophysical parameters, and accurate geometrical sizes of the interconnect elements.
Another object of this invention is to provide a process for producing interconnections which does not require chemical etching and which is relatively ecologically safe.
Another object of this invention is to provide a novel process for the production of interconnections such that a greater breadth of useful geometric designs can be achieved, the incorporation of passive resistive and capacitive elements into any level of the interconnect system may be accomplished without concern for compatibility with metal wiring boards, and which increases the quality, reliability and packing density of microelectronic devices and ensures their high resistance to mechanical, temperature and electromagnetic effects.
Another object of this invention is to provide a multilevel system of interconnections comprising of only metallic aluminum, barrier aluminum oxide and porous aluminum oxide layers, that is, a system in which aluminum oxides are used to insulate metallic aluminum interconnects.
Another object of this invention is to provide a process which can ensure the planarity of each level of the multilevel system and which thus enhances the insulating properties of the interlevel and intercomponent insulator, the reproducibility of the electrical parameters and the reliability of the interconnections of the electronic parts.
Another object of this invention is to provide a process for the fabrication of a multilevel interconnected system which can be easily automated and achieves high reproducibility of the device parameters, yet does not require large floor-spaces, special equipment or scarce materials. The process should utilize minimal quantities of materials and inexpensive metallization materials, such as aluminum, valve metals and their anodic oxides, and should employ standard vacuum and photolithography equipment as found in present day electronic enterprises.
The foregoing has outlined some of the pertinent objects of the invention. These objects should be construed to merely illustrative of some of the more prominent features and applications of the intended invention. Many other beneficial results can be attained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention can be seen by reference to the following detailed description of the preferred embodiment in addition to the scope of the invention defined by the claims taken in conjunction with the accompanying drawings.